1. Field of the Invention
The present invention relates to dual resolution control of display panels.
2. Description of the Related Art
Display panels are driven by a series of panel control signals, such as the panel control signals 105˜108 depicted in FIG. 1. These panel control signals provide a series of pulses, which are used to switch data signals into correct data lines for correct pixels, and to load data signals into pixels on each scan line. Panel control signals are usually generated from shifting signals, such as the shifting signals 101˜104 in FIG. 1.
FIG. 2 is a schematic diagram showing part of the conventional control circuit 200 for generating panel control signals. The control circuit 200 comprises shift registers, logic gates and a switching network 100. Each of the shift registers SR1˜SR4 receives clock signals CK1 and CK2, as well as a corresponding shifting signal (101˜104) from a previous shift register. Each of the shift registers also outputs its own shifting signal to a next shift register, to a corresponding logic gate, and to a next logic gate. The clock signals CK1 and CK2 have the same frequency and are always in opposite phases, as depicted in FIG. 3. Each of the logic gates G1˜G4 receives two shifting signals and outputs a panel control signal (105˜108). The logic gates G1˜G4 in the control circuit 200 are AND gates to generate panel control signals with high pulses. Thus, logic gates G1˜G4 generate the panel control signals 105˜108 according to the shifting signals 101˜104, which are generated from switching network 100.
For many applications, it is desirable to have display panels support two resolutions, usually a high resolution, such as the VGA (video graphic array) resolution of 640 columns by 480 rows, and a low resolution, such as the QVGA (quarter video graphic array) resolution of 320 columns by 240 rows. In this regard, low resolution typically is achieved by filling identical data into adjacent pixels, so that four adjacent pixels are consolidated into a larger pixel. To implement such low resolution, panel control signals typically are synchronized into pairs, such as shown by the panel control signals 401˜404 in FIG. 4. Notably, the interconnection among shift registers and logic gates typically has to be adjusted for changing resolution. The adjustment is usually implemented with a switching network.
Regarding switching network 100, in some conventional designs, half of the existing shift registers may not used when the display panel scans upward or downward in the low resolution mode. Unused shift registers are in a floating state and tend to accumulate charges. If the voltage generated by accumulated charges is higher than the highest operating voltage of the display panel or lower than the lowest operating voltage of the display panel, there can be errant operations in the display panel, potentially causing abnormalities.